(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of metallization resulting in improved electromigration resistance in the manufacture of integrated circuits.
(2) Description of the Prior Art
The electromigration endurance of metal lines is closely related to metal cross sectional area, the metal material, operation temperature, current density, etc. In sub half-micron devices, the metal lines have been shrunk as much as possible to reduce chip area. Therefore, high current density in metal lines becomes a major issue for electromigration resistance.
The applied voltage in devices generates an electrical field inside the conducting material as well as on the dielectric. The magnitude of the current density in the conducting material is proportional to the existing electrical field and the conductivity of the material. That is, J=.sigma.E=.sigma.(-dV) where J=current density,
E=electrical field,
V=electrical potential,
.sigma.=conductivity, and
d=the directional derivative.
The current density can be reduced if the electrical field is reduced. This will improve the electromigration endurance. The Mean Time to Failure (MTF) of a metal line is proportional to J.sup.-n e.sup.(Ea/RT), where Ea is the activation energy of the metal.
U.S. Pat. No. 4,812,419 to Lee et al describes a method of using a strip of high resistivity material to line the via hole connecting two metal lines to assure more uniform current flow. However, this method does not fully solve the current density problem at the corners of metal lines.